Reduct computation: from the algorithm to the FPGA
Doctoral work on an NP-hard combinatorial problem, attacked simultaneously in algorithm design and in hardware.
The problem. Computing all reducts of a decision system — the minimal attribute subsets that preserve its discernibility — is NP-hard. The naive approach enumerates the power set, and the cost is not something you optimise your way out of with better code.
Two fronts at once. On the algorithmic side, GCreduct prunes the search space using gap elimination and attribute contribution; MinReduct computes all the shortest reducts without enumerating the rest. On the hardware side, a co-designed FPGA platform accelerates the computation of irreducible testors.
Why it still matters here. It is the same instinct that produced everything else on this page: when a computation is expensive, the answer is rarely a bigger machine. It is a better algorithm, the right place to run it, and the willingness to design both.
- FPGA
- VHDL
- C
- Rough set theory